Mapping Switch-Level Simulation onto Gate-Level Hardware Accelerators
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Abstract or Description
In this paper, we present a framework for performing switch-level simulation on hardware accelerators. A symbolic analyzer preprocesses the MOS network into a functionally equivalent Boolean representation. The analyzer thus converts switch-level simulation into a task of evaluating Boolean expressions. Our approach maps the Boolean representation into the instruction set of the hardware accelerator. The resultant framework supports switch-level simulation on a class of hardware accelerators that traditionally have been limited to gate-level simulation.