Symbolic Functional and Timing Verification of Transistor-Level Circuits
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Abstract or Description
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaustively verify a medium-sized modern logic block. Static analysis can handle much larger circuits but is not robust with respect to variations from standard circuit structures. Our approach applies symbolic simulation to analyze a circuit over all input combinations without these limitations. We present a prototype simulator (Sir-Sim) and experimental results. We also discuss using SirSim to verify an industrial design which previously required a specialpurpose verification methodology.