Title

ACV: An Arithmetic Circuit Verifier

Date of Original Version

1996

Type

Working Paper

Rights Management

All Rights Reserved

Abstract or Description

Based on a hierarchical verification methodology, we present an arithmetic circuit verifier ACV, in which circuits expressed in a hardware description language, also called ACV, are symbolically verified using Binary Decision Diagrams for Boolean functions and multiplicative Binary Moment Diagrams (*BMDs) for wordlevel functions. A circuit is described in ACV as a hierarchy of modules. Each module has a structural definition as an interconnectionof logic gates and other modules. Modules may also have functional descriptions, declaring the numeric encodings of the inputs and outputs, as well as specifying their functionality in terms of arithmetic expressions. Verification then proceeds recursively, proving that each module in the hierarchy having a functional description, including the toplevel one, realizes its specification. The language and the verifier contain additional enhancements for overcoming some of the difficulties in applying *BMDbased verification to circuits computing functions such as division and square root. ACV has successfully verified a number of circuits, implementing such functions as multiplication, division, and square root, with word sizes up to 256 bits.