Bit-Level Analysis of an SRT Divider Circuit

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Working Paper

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Abstract or Description

It is impractical to verify multiplier or divider

circuits entirely at the bitlevelusing ordered Binary Decision Diagrams (BDDs), because the BDD representations for these functions grow exponentially with the wordsize. It is possible, however, to analyze individual stages of these circuits using BDDs. Such analysis can be helpful when implementing complex arithmetic algorithms. As ademonstration, we showthat Intel could have used BDDs to detect erroneous lookup table entries in the Pentium(TM)floating point divider. Going beyond verification, we show that bitlevelanalysis can be used to generate a correct version of the table.