Formal Verification of Memory Circuits by Switch-Level Simulation

Date of Original Version




Abstract or Description

A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits implementing the system specification will produce a particular response to a sequence of simulation commands. Three valued modeling, where the third state X

indicates a signal with unknown digital value, can greatly reduce the number of patterns that need to be simulated for complete verification. As an extreme case, an N-bit random-access memory (RAM) can be verified by simulating just O(N log N)

patterns. This approach to verification is fast, requires minimal attention on the part of the user to the circuit details, and can utilize more sophisticated circuit models than other approaches to formal verification. The technique has been applied to a CMOS static RAM design using the COSMOS switch level simulator. By simulating many patterns in parallel, a massivelyparallel computer can verify a 4K RAM in under 6 minutes.