Date of Original Version
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Abstract or Description
In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared DRAM mainmemory. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to provide a tight upper bound on the worst-case memory interference in a COTS-based multi-coresystem. We explicitly model the major resources in the DRAM system, including banks, buses and thememory controller. By considering their timing characteristics, we analyze the worst-case memoryinterference delay imposed on a task by other tasks running in parallel. To the best of our knowledge, this is the first work bounding the request re-ordering effect of COTS memory controllers. Our work also enables the quantification of the extent by which memory interference can be reduced by partitioning DRAM banks. We evaluate our approach on a commodity multi-core platform running Linux/RK. Experimental results show that our approach provides an upper bound very close to our measured worst-case interference.
Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014, 145-154.