Date of Original Version

6-2012

Type

Conference Proceeding

Published In

Proceedings of SRC TechCon

Rights Management

Copyright 2012 SRC

Abstract or Description

As nanoscale lithography challenges mandate greater pattern regularity and commonality for logic and memory circuits, new opportunities are created to affordably synthesize more powerful smart memory blocks for specific applications. Leveraging the ability to embed logic inside the memory block boundary, this paper demonstrates the synthesis of smart memory architectures that exploits the inherent memory address patterns of the back projection algorithm to enable efficient image reconstruction at minimum hardware overhead. An end-to-end design framework in sub-20nm CMOS technologies was constructed for the physical synthesis of smart memories and exploration of the huge design space. The experimental results show that customizing memory for the computerized tomography parallel back projection can achieve more than 30% area and power savings with marginal sacrifice of image accuracy.

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