Date of Award

Winter 2-2017

Embargo Period


Degree Type

Dissertation (CMU Access Only)

Degree Name

Doctor of Philosophy (PhD)


Electrical and Computer Engineering


Jeyanandh Paramesh


With the explosive growth of mobile traffic demand, the contradiction between capacity requirements and spectrum shortage becomes the bottleneck towards high date rate wireless communication systems. The millimeter-wave (mm-wave) frequency bands have recently emerged as a viable option to meet the exploding demand for wireless multimedia content over short ranges. Frequency synthesizers that can tune over wide bandwidths in finely spaced steps are essential components in wireless mm-wave applications. With all the advantages of all-digital frequency synthesizers, they remained restricted to low gigahertz operating frequencies since the design of DCOs, TDCs, and frequency dividers operating at mm-wave frequency poses enormous challenges, and the mitigation of those challenges remains an open problem. This research explores the feasibility, advantages, implementation, and testing of millimeter-wave fractional-N digital frequency synthesizers. In addition, it proposes several design techniques to overcome the design challenges of the constituent blocks in mm-wave ADPLL’s, thereby enhancing performance by reducing spurs, increasing tuning range and frequency resolution. While, the proposed architectures and techniques is suitable for all mm-wave applications below 100 GHz, a 60 GHz frequency synthesizer is implemented in this work as an example to validate the proposed techniques. During the investigation of millimeter-wave Fractional-N digital frequency synthesizers, several solutions are proposed and validated.

Available for download on Wednesday, March 06, 2019