Date of Award

9-2010

Embargo Period

10-19-2012

Degree Type

Dissertation

Degree Name

Doctor of Philosophy (PhD)

Department

Electrical and Computer Engineering

Advisor(s)

Lawrence T. Pileggi

Abstract

Process variations in advanced CMOS process nodes limit the benefits of scaling for analog designs. In the presence of increasing random intra-die variations, mismatch becomes a significant design challenge in circuits such as comparators. In this dissertation, the statistical element selection (SES) methodology that was first proposed in [1] is analyzed in detail and extended to accommodate a broader spectrum of circuits and systems. SES relies on choosing a subset of selectable circuit elements (e.g., input transistors in a comparator) to achieve the desired specification (e.g., o set). Silicon results from a 65nm bulk CMOS test chip demonstrate that it can achieve an order of magnitude better matching than both redundancy and simple scaling given the same core circuit area. To demonstrate its efficacy, we applied SES to enable a novel ash ADC topology in 45nm SOI CMOS that operated at 1GS=s and achieved 4.6bits of ENOB with a figure of merit of 160fJ=step. SES is also applied to an array of microelectromechanical resonators to improve the expected yield of RF MEMS lters.

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