Date of Award

Fall 9-2017

Embargo Period

9-28-2019

Degree Type

Dissertation (CMU Access Only)

Degree Name

Doctor of Philosophy (PhD)

Department

Electrical and Computer Engineering

Advisor(s)

Jeyanandh Paramesh

Second Advisor

Larry Pileggi

Abstract

The rapid progress of scaling and integration of modern complimentary metal oxide semiconductor (CMOS) technology motivates the replacement of traditional analog signal processing by digital alternatives. Thus, analog-to-digital converters (ADCs), as the interfaces between the analog world and the digital one, are driven to enhance their performance in terms of speed, resolution and power efficiency. However, in the presence of imperfections of device mismatch, thermal noise and reduced voltage headroom, efficient ADC design demands new strategies for design, calibration and optimization. Among various ADC architectures, successive-approximation-register (SAR) ADCs have received renewed interest from the design community due to their low hardware complexity and scaling-friendly property. However, the conventional SAR architecture has many limitations for high-speed, high-resolution applications. Many modified SAR architectures and hybrid SAR architectures have been reported to break the inherent constraints in the conventional SAR architecture. Loop-unrolled (LU) SAR ADCs have been recognized as a promising architecture for high-speed applications. However, mismatched comparator offsets introduce input-level dependent errors to the conversion result, which deteriorates the linearity and limits the resolution and the resolution of most reported SAR ADCs of this kind are limited to 6 bits. Also, for high-resolution SAR ADCs, the comparator noise specification is very stringent, which imposes a limitation on ADC speed and power-efficiency. Lastly, capacitor mismatch is an important limiting factor for SAR ADC linearity, and generally requires dedicated calibration to achieve efficient designs in terms of power and area. In this work, we investigate the impacts of offset mismatch, comparator noise and capacitor mismatch on high-speed SAR ADCs. An analytical model is proposed to estimate the resolution and predict the yield of LU-SAR ADCs with presence of comparator offset mismatch. A background calibration technique is proposed for resolving the comparator mismatch issue. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7-dB to 42.9-dB. The ADC consumes 640 μW from a 1.2 V supply with a Figure-of-Merit (FoM) of 37.5-fJ/conv-step. Moreover, the bit-wise impact of comparator noise is studied for LU-SAR ADCs. Lastly, an extended statistical element selection (SES) calibration technique is proposed to calibrate the capacitor mismatch in SAR ADCs. Based on these techniques, a high-resolution, asynchronous SAR architecture employing multiple comparators with different speed and noise specifications to optimize speed and power efficiency. A 12-bit prototype ADC is fabricated in a 1P9M 65nm CMOS technology, and fits into an active area of 500 μm × 200 μm. At 125 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 64.4 dB and a spurious-free-dynamic-range (SFDR) of 75.1 dB at the Nyquist input frequency while consuming 1.7 mW from a 1.2 V supply. The resultant figure-of-merit (FoM) is 10.3 fJ/conv-step.

Available for download on Saturday, September 28, 2019

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