Date of Original Version

9-2000

Type

Conference Proceeding

Published In

2000 International Conference on Computer Design, 2000. Proceedings. ,pp.423-429, 2000

Abstract or Description

In this paper, we present a fast and efficient compilation methodology for pipeline reconfigurable architectures. Our compiler back-end is much faster than conventional CAD tools, and fairly efficient. We represent pipeline reconfigurable architectures by a generalized VLIW-like model. The complex architectural constraints are effectively expressed in terms of a single graph parameter: the routing path length (RPL). Compiling to our model using RPL, we demonstrate fast compilation times and show speedups of between 10x and 200x on a pipeline reconfigurable architecture when compared to an UltraSparc-II

DOI

10.1109/ICCD.2000.878318

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