Date of Original Version

8-2001

Type

Conference Proceeding

Abstract or Description

Speedups of coupled processor-FPGA systems over traditional microprocessor systems are limited by the cost of hardware reconfiguration. In this paper we compare several new configuration caching algorithms that reduce the latency of reconfiguration. We also present a cache replacement strategy for a 3-level hierarchy. Using the techniques we present, total latency for loading the configurations is reduced, lowering the configurable overhead.

DOI

10.1007/3-540-44687-7_20

Share

COinS