Date of Original Version



Conference Proceeding

Abstract or Description

The temporal logic model algorithm of E.M. Clarke et al. (ACM Trans. Prog. Lang. Syst., vol.8, no.2, p.244-63, 1986) is modified to represent a state graph using binary decision diagrams (BDDs). Because this representation captures some of the regularity in the state space of sequential circuits with data path logic, one is able to verify circuits with an extremely large number of states. This new technique is demonstrated on a synchronous pipelined design with approximately 5×1020 states. The logic that is used to specify circuits is a propositional temporal logic of branching time, called CTL or Computation Tree Logic. The model checking algorithm handles full CTL with fairness constraints. Consequently. it is possible to handle a number of important liveness and fairness properties. which would otherwise not be expressible in CTL. The method presented is not necessarily a replacement for brute-force state-enumeration methods but an alternative that may work efficiently when the brute force methods fail