Date of Original Version

1-2003

Type

Conference Proceeding

Abstract or Description

We describe an algorithm to verify a hardware design given in Verilog using an ANSI-C program as a specification. We use SAT based BoundedModel Checking [1] in order to reduce the equivalence problem to a bit vector logic decision problem. As a case study, we describe experimental results on a hardware and a software implementation of the data encryption standard (DES) algorithm.

DOI

10.1109/ASPDAC.2003.1195033

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