Date of Original Version
8-2006
Type
Conference Proceeding
Published In
F. Pfenning (Ed.): RTA 2006, LNCS 4098, pp. 1–3, 2006.
Abstract or Table of Contents
Most successful automated formal verification tools are based on a bit-level model of computation, where a set of Boolean state variables encodes the system state. Using powerful inference engines, such as Binary Decision Diagrams (BDDs) and Boolean satisfiability (SAT) checkers, symbolic model checkers and similar tools can analyze all possible behaviors of very large, finite-state systems.